Challenges in Interconnection Network Design In the Era of Multiprocessor and Massively Parallel Microchips

Custom microchips housing many simple processors have long been used in the design ofmassively parallel computers. Commercially available SIMD!arallel systems of the late 1980s already containe tens of bit-serial processors on each chip and more recent products offer hundreds of processors per chip. Use of microchips housing multiple general-purpose processors. with large memories. has also been proposed. No matter how many processors we can put on one chip. the demandfor greater performance will sustain the need for integrating multiple chips into systems that offer even higher levels of parallelism. With tens to tens of thousands of on-cfiip processors afforded by billion-transistor chips. small-scale parallel systems built of powerful general-purpose processors. as well as multimillion-node massively parallel systems. will become not only realizable but also quite cost-effective. Our thesis is that design challenges for single-chip mUltifrocessors and massively parallel systems. as wei as their use in synthesizing even larger parallel systems. are not fundamentally different from those currently facing parallel computer designers. given that interconnects already constitute the limiting factor. Either way. we need to rely on multilevel (hierarchical or recursive) parallel architectures. The difference is in scale rather than substance. with the requisite theories and design strategies already in place.